The present invention relates to lowering of the voltage of a power-supply semiconductor integrated circuit.
An existing voltage detector or voltage regulator comprising a CMOS transistor uses an N-type gate electrode for the gate electrode of an NMOS transistor of the CMOS transistor and an N-type gate electrode for the gate electrode of a PMOS transistor of the CMOS transistor.
FIG. 3 shows a circuit block diagram of a voltage detector. The voltage detector comprises a reference voltage circuit 301; a voltage division circuit 302, a voltage comparison circuit 303, and an output circuit 304. The reference voltage circuit 301 comprises a depletion-type NMOS transistor and an enhancement-type NMOS transistor which mutually connect in series between a power supply line 202 and a ground line 201 and has a function for outputting a constant voltage to the joint A 111. The voltage division circuit 302 comprises a plurality of series resistances connected between the power supply line 202 and the ground line 201 and has a function for dividing a power supply voltage by using a joint B 112 as a separating point. The voltage comparison circuit 303 comprises PMOS transistors and NMOS transistors, which are connected between the power supply line 202 and the ground line 201, connects with the reference voltage circuit 301 at the joint A 111 and with the voltage division circuit 302 at the joint B 112, compares the voltage difference between the joint A 111 and the joint B 112 and has a function of outputting a voltage equal to a power supply voltage to a joint C 113 when the voltage at the joint B 112 is lower than the voltage at the joint A 111.
The output circuit 304 comprises an inverter constituted by combining a PMOS transistor with an NMOS transistor, in which the source of the PMOS transistor connects with the power supply line 202, the drain of the PMOS transistor connects with the drain of the NMOS transistor, and the source of the NMOS transistor connects with the ground line 201.
The voltage comparison circuit 303 and the gate electrode of the inverter are connected to each other at the joint C 113. When the output of the voltage comparison circuit 303 is received by the gate electrodes of the PMOS and NMOS transistors, the drain joint between the PMOS and NMOS transistors has a function of outputting a voltage equal to the power supply voltage.
A detection voltage is determined by the reference voltage which is outputted by the reference voltage circuit 301 and the ratio of the resistance of high-resistance polysilicon, and a desired output voltage can be obtained by a polysilicon fuse built. Moreover, high-resistance polysilicon with a high resistance value is used to decrease current consumption and the high-resistance polysilicon and a CMOS transistor are indispensable components for a CMOS power supply IC.
The voltage detector has a function for decreasing an output voltage to 0 V when the power supply voltage is equal to the detection voltage or lower (e.g. 0.8 V or lower).
FIG. 6 shows a circuit block diagram of the voltage regulator. The voltage regulator comprises a reference voltage circuit 311, a voltage division circuit 312, a voltage comparison circuit 313, and an output circuit 314. The reference voltage circuit 311 comprises a depletion-type NMOS transistor and an enhancement-type NMOS transistor which mutually connect in series between a power supply 212 and an earthing line 211 and has a function of a constant output voltage to the joint A 121.
The voltage division circuit 312 comprises a plurality of series resistances connected between the power supply line 212 and the ground line 211, and has a function of dividing a power supply voltage by using a joint B 122 as a separating point.
The voltage comparison circuit 313 comprises PMOS transistors and NMOS transistors, which are connected between the power supply line 212 and the ground line 211, and connects with the reference voltage circuit 311 at the joint A 121 and with the voltage division circuit 312 at the joint B 122, and compares the voltage difference between the joint A 121 and the joint B 122 and has a function of outputting the gate controlled voltage to the output circuit 314.
The output circuit 314 comprises a PMOS transistor or an NMOS transistor. When the circuit 314 comprises the output PMOS transistor, it is constituted so as to connect the source with the power supply line 212 and the drain of the PMOS with a voltage division circuit 312.
When the output circuit 314 comprises the NMOS transistor, it is constituted so as to connect the drain with the power supply line 212 and the source of the NMOS transistor with the voltage division circuit 312.
Moreover, the output circuit 314 is constituted so as to connect the voltage comparison circuit 313 with the gate electrode of the PMOS or NMOS transistor at the joint C 123 and receive the output of the voltage comparison circuit 313 by the gate electrode of the PMOS or NMOS transistor, and has a function of outputting a voltage to an output terminal 133 connected to the drain of the PMOS transistor or the source of the NMOS transistor.
The voltage regulator has a function of continuously outputting a constant output voltage even if a power supply voltage or a load fluctuates.
FIG. 23 shows an existing reference voltage circuit used for a voltage detector or voltage regulator. The reference voltage circuit comprises a depletion-type NMOS transistor 401 and an enhancement type NMOS transistor 402 which mutually connect in series between a power supply line 222 and a ground line 221 and has a function of outputting a constant output voltage to the joint A 161.
The depletion-type NMOS transistor 401 connects the gate with the source to equalize the potential with that of a substrate and connects the source with the drain of the enhancement-type NMOS transistor. The enhancement-type NMOS transistor 402 connects the gate with the drain to equalize the potential of the substrate with that of the source.
Moreover, the drain of the depletion-type NMOS transistor 401 connects with the power supply line 222, the source of the enhancement-type NMOS transistor connects with the ground line 221, and the joint A 161 between the depletion-type transistor 401 and the enhancement-type transistor 402 is used as an output terminal.
[0004]--Existing Example (Fabrication Method)
In general, an existing voltage detector and a voltage regulator comprising a CMOS transistor respectively are fabricated differently from each other by forming a high resistance and a gate electrode with a polysilicon film and changing the amount of impurities to be introduced into the polysilicon film.
An existing method for fabricating high-resistance polysilicon and a polysilicon-gate CMOS transistor on the same substrate is described below by taking a P substrate as an example and referring to FIGS. 20 to 22.
An N well 2 is first formed on a P-type silicon substrate 1 through ion implantation and thermal diffusion and thereafter, a P-type region 3 and an N-type region 4 are formed through ion implantation to separate devices. Then, a field oxide film 5 and a gate oxide film 6 are formed {FIG. 21A} ions are implanted into a channel region for transistor threshold control {FIG. 2B} and a polysilicon film 7 is deposited {FIG. 21C}. Then, ions are implanted into high-resistance polysilicon 8 to control the resistance value {FIG. 21D}, a CVD oxide film 9 wider than a portion serving as the high-resistance polysilicon 8 is deposited, the pre-deposition of phosphorus is performed, and high-concentration phosphorus is diffused in the polysilicon film {FIG. 21E}. Then, the oxide film is removed from the polysilicon and thereafter the high-resistance polysilicon 8 is formed through etching {FIG. 21F}. Polysilicon gate electrodes 10 and 11 are then formed through etching by using another mask {FIG. 22A}, and finally ions are implanted into an N-channel-side source and drain region 12 and a P-channel-side source and drain region 13 {FIG. 22B} and provided with thermal annealing to complete the high-resistance polysilicon 8 and the polysilicon-gate CMOS transistor {FIG. 22C}.
For an existing semiconductor device, the gate electrodes of PMOS and NMOS transistors are the N type. Therefore, the PMOS transistor is necessarily of the buried channel type. A buried-channel-type MOS transistor has disadvantages of inferior channel leak current characteristics, more leak current than the surface channel type, short-channel effect and the disadvantage that it is difficult to control the threshold voltage. Particularly, the necessity for low power consumption under operation is larger than the case of a general IC because a voltage detector and voltage regulator continuously operate. Moreover, because energy is supplied to the buried-channel-type MOS transistor from a battery, low-voltage operation is necessary. Therefore, it is necessary to lower the threshold voltage of the MOS transistor to operate a semiconductor device at a low voltage. However, because the existing buried-channel-type MOS transistor has a large channel leak current, low-voltage operations are difficult to realize. Moreover, because channel leak current tends to increase at a high temperature, low-voltage operations are more difficult than those at the room temperature.
Furthermore, it is necessary to lower the reference voltage from the reference voltage circuits 301 and 311 in order to operate the semiconductor device at a low voltage. In the case of the existing reference voltage circuits 301 and 311, the reference voltage to be outputted is determined by the sum of the threshold voltage of the enhancement-type MOS transistor 401 and that of the depletion-type MOS transistor of the circuits. Therefore, the threshold voltage must be lowered to obtain a low reference voltage. However, lowering the reference voltage is limited due to the above channel leak current.
Furthermore, the existing method for fabricating a semiconductor device comprising high-resistance polysilicon and a polysilicon-gate CMOS transistor has the following problems. That is, though introduction of impurities into the polysilicon gate 8 is accomplished by ion implantation, introduction of impurities into the polysilicon gates 10 and 11 is accomplished by the diffusion implantation method called pre-deposition. Therefore, to perform the pre-deposition of phosphorus, high-concentration phosphorus must be prevented from entering a high-resistance region by covering the high-resistance region with a CVD oxide film. Moreover, because the etching rate differs due to the phosphorus concentration, it is impossible to etch both the high resistance polysilicon 8 and the polysilicon gates 10 and 11 at the same time. Therefore, a problem occurs that the number of processes increases.
Furthermore, as a method for solving the above problem, boron ions are implanted into the gate electrode of a PMOS transistor when the gate electrode of an NMOS transistor uses an N-type gate electrode and the gate electrode of the PMOS transistor uses a P-type gate electrode. However, there are problems that boron ions penetrate into a channel region due to implantation of the ions into the gate electrode, the boron ions implanted into the gate electrode penetrate into the channel region, or the gate electrode is depleted due to insufficient thermal anneal. Moreover, to keep the thermal annealing temperature low, it is necessary to increase the phosphorus concentration of the inter-layer insulating film PSG 20. When increasing the phosphorus concentration, however, a problem occurs that the phosphorus in the inter-layer insulating film PSG 20 diffuse in the high-resistance polysilicon 8 to decrease the resistance value of the high-resistance polysilicon 8.
The present invention is made to solve the above problems and its first object is to provide a voltage detector and a voltage regulator which operate at a low voltage and a low current consumption.
It is the second object of the present invention to lower the output reference voltage of a reference voltage circuit used for a voltage detector and a voltage regulator.
It is the third object of the present invention to provide a method for efficiently fabricating a semiconductor device when forming a high-resistance polysilicon gate and a CMOS transistor on the same substrate.
It is the fourth object of the present invention to provide a semiconductor device fabrication method for preventing boron from penetrating into a channel region when forming a P-type polysilicon gate through ion implantation and a polysilicon gate from being depleted when forming polysilicon gate through ion implantation.
It is the fifth object of the present invention to provide a semiconductor device fabrication method for preventing the resistance value change of high-resistance polysilicon due to diffusion of phosphorus in an inter-layer insulating film PSG.